John Wiley & Sons are proposing to publish the new, 3rd edition of my book “VHDL for Logic Synthesis” on 8 April this year.
See the Amazon pages for prices and ordering details:
This has been a long time coming. Plans for a third edition were made in June 2009. The idea was to bring the book, now 12 years old, up to date with modern methods and with extensions to the language and libraries added by the VHDL-2008 re-standardisation.
I’m really pleased with the result, despite the long development time from plan to publication. I think this is a significant update which introduces themes like fixed-point and floating-point synthesis using the new packages added in 2008.
The new examples have been tested using Mentor’s ModelSim for simulation, Altera’s Quartus and Xilinx 11 for synthesis. However, the new synthesis packages are also available for Cadence ncvhdl, Synopsys, Synplicity and Leonardo Spectrum so all the examples should work with those tools as well.
For more on this, see the page on my website “VHDL for Logic Synthesis”.