“VHDL for Logic Synthesis” is a text book on the VHDL language which has been in print since 1995, first with McGraw-Hill and then as a revised second edition published in 1998 by John Wiley & Son.
During 2010 I have been working on substantial updates to the book, including VHDL-2008 additions, fixed-point and floating-point arithmetic.
Plans for a third edition were made in June 2009. The idea was to bring the book, now 12 years old, up to date with modern methods and with extensions to the language and libraries added by the VHDL-2008 re-standardisation.
I’m really pleased with the result, despite the long development time from plan to publication. I think this is a significant update which introduces themes like fixed-point and floating-point synthesis using the new packages added in 2008.
The new examples have been tested using Mentor’s ModelSim for simulation, Altera’s Quartus and Xilinx 11 for synthesis. However, the new synthesis packages are also available for Cadence ncvhdl, Synopsys, Synplicity and Leonardo Spectrum so all the examples should work with those tools as well.
VHDL for Logic Synthesis, Third Edition was published in April 2011.
See the following pages for more information:
See also any posts on the subject of VHDL.