This is the preface to the book as published.
The motivation for writing this book originally came from my own frustration at the lack of a synthesis-orientated book when I was learning VHDL. Not only was there a lack of information on the synthesis subset, but I found that most books on VHDL had a common problem: they described absolutely everything in an indiscriminate way, and left the reader to sort out which bits were relevant and useful. It was extremely difficult to deduce the synthesis subset from this approach.
In this book, I cover the features of VHDL that you need to know for logic synthesis, from a hardware designer’s viewpoint. Each feature of the language is explained in hardware terms and the mapping from VHDL to hardware is shown. Furthermore, only the synthesisable features are presented and so there is no possibility of confusion between synthesisable and non-synthesisable features.
The exception to this rule is the chapter on test benches. Even hardware designers using the language exclusively for logic synthesis will have to write test benches and since these are not synthesised, the whole language becomes available (but not necessarily useful). So the test bench chapter introduces those parts of the language that are relevant and useful for writing test benches.
The reason that a book like this is necessary is that VHDL is a very large and clumsy language. It suffers from design-by-committee and as a result is difficult to learn, has many useless features, and I can say from my own experience, is extremely difficult to implement. I am not a champion of VHDL, but I recognise that it is still probably the best hardware description language for logic synthesis that we have. I hope that, by sharing what I have learnt of the language and how it is used for synthesis, I can help you avoid the many pitfalls that lie in wait.
I have this perspective on VHDL because I started my career as an Electronics Engineer, specialising in Digital Systems Design and gaining a BSc and PhD from the Department of Electronics at Southampton University, UK, in 1983 and 1987 respectively. However, I then moved into software engineering, but using my hardware background to develop software within the Electronics Design Automation industry. I have been working on VHDL and Electronic Design Automation using VHDL since 1988.
Initially I worked on logic synthesis systems, first for Plessey Research Roke Manor which is now a part of Siemens’ UK operation. Then, in 1992 our then manager and CEO-to-be Jim Douglas arranged a management buyout of the synthesis technology that we had developed, supported by venture-capital funding from MTI Partners. Thus was born TransEDA Limited.
He took with him the key engineers for the project, and so I became one of the founder members of the new company. I was Research Manager for the new company and continued working on the logic synthesis project.
Our intention was to develop our in-house logic synthesis tool to commercial standard and sell it under the name TransGate. One of my first tasks was to help develop a VHDL front-end to the tool to replace the existing proprietary language front-end. I was very proud of the results that we achieved – TransGate had a very comprehensive support for the language, competitive with the best in the market at the time and considerably better than the majority of tools.
When we first released TransGate, we expected that engineers would take to VHDL easily, so we concentrated on the purely technical aspects of developing the synthesis algorithms. However, it gradually became apparent from feedback that users were experiencing problems with using VHDL for logic synthesis due to the learning curve associated with what was, at that time, a completely new hardware design paradigm.
As a consequence of this realisation, in 1992 I developed a new training course, offered as a public or on-site course and called ‘VHDL for Hardware Design’. This course was based on my inside knowledge of how VHDL is interpreted by a synthesiser and also on the practical problem solving that I had been involved with as part of the company’s customer support programme.
The first edition of this book, published in 1995 by McGraw-Hill, grew out of that training course. Much of the text and some of the examples were taken straight from the course. However, there is far more to a book than can be covered in a three-day long training course, so the book covered more material in far more detail than was possible in the training course.
Furthermore, at the time of writing the first edition, there was an international standardisation effort to define a standard set of arithmetic packages and common interpretation and subset for VHDL for logic synthesis. Although this standardisation was still some way from completion at the time, nevertheless there were some aspects of logic synthesis from VHDL which had a wide consensus and this was used to inform the writing of the book.
Back at TransEDA, we were finding that the logic synthesis market niche was not only already occupied but comprehensively filled by well-established companies and we made little progress in selling our synthesis tools.
Fortunately, we branched off into code coverage tools and created a niche for ourselves in this market instead. I became the lead systems developer for the VHDLCover system. Through this project, which involved a lot of collaboration with customers, I gained experience of scores of large synthesisable VHDL designs involving hundreds of designers working in many different styles.
This change in direction of our company had a strong influence on the second edition of this book which was published in 1998 by John Wiley and Sons. Three years had passed and the standards committee had at last ratified a standard for the synthesis packages. Furthermore, exposure to many other designers’ work allowed me to take a broader view of the use of synthesis and its place in the design cycle. This made the book more user-orientated than the first edition, which did tend to dwell too much on the way that synthesisers worked. I think that the change in emphasis (slight though it was) improved the book significantly.
I left TransEDA in 1999, and since I left the company has gone bust, unfortunately disbanding the development team. However, the code coverage technology and the company name has been bought out and so TransEDA still sells VHDLCover but now under the name VN-Cover.
After TransEDA, I joined Southampton University and became a founding member of the university spin-off company Leaf-Mould Enterprises (LME). LME was formed with the intention of developing commercial behavioural synthesis systems using VHDL and based on a research programme within my old department, the Department of Electronics and Computer Science. I was responsible for the VHDL library manager, compiler and assembler which produced the concurrent assembly code from which behavioural synthesis was performed. Unfortunately funding problems led to the demise of LME in 2001.
Since then I have become a self-employed consultant, working in a diversified range of fields: programmer, web applications designer, systems engineer and counsellor.
It is 12 years since the publication of the second edition and it is interesting to see what has changed in the field of synthesis. The main change is that designers are moving on to system-level synthesis using C-like languages such as System Verilog, SystemC and Handel-C. However, there is clearly still a role for logic synthesis using VHDL for those who need more control over their design or, for that matter, as the synthesis engine for higher-level tools. There are now a plethora of logic synthesis tools available, for both ASIC and FPGA design.
However, VHDL itself has hardly changed at all for most of that time, with just minor tweaks to the language in 2000 and 2002. Then, in 2008, a major update was published to address a wide range of problems and to expand the range of pre-defined packages delivered with the language. Many of these changes affect synthesis. So, the time has come for a third edition of the book to reflect these changes. I have updated the whole book to reflect the current position, where the full VHDL-2008 standard is not yet available in any commercial tool, either for simulation or for synthesis, but some of the synthesis-specific features are gradually becoming available, either incorporated into the synthesis tools or as downloadable add-ons.